1. Field of the Invention
The present invention generally relates to the manufacture of semiconductor integrated circuits and modules and, more particularly, to the formation of structures therein which enhance signal propagation and improve performance of such devices.
2. Description of the Prior Art
It has long been recognized that increases in integration density provide significant performance enhancements and increased chip functionality as well as manufacturing economy in integrated circuits. Accordingly, many advances have been achieved in lithographic processes in order to reduce the minimum feature sizes which define the electronic elements of such devices. The minimum feature sizes now possible and foreseeable, however, require optimization of the lithographic exposure tool to compensate for various physical effects which are unavoidable such as exposure dose variation due to scattering of photons or electrons within the resist. Therefore, it is very difficult, if not impossible, to accurately produce features of different sizes in the same resist or lithographic level consistent with high integration density.
Nevertheless, optimum performance and integration density of integrated circuits often cannot be achieved without provision of elements, including conductors of differing sizes, each adapted to the specific function of that element, such as current capacity, thermal conduction and the like. For example, transistors used to precharge circuits to provide increased switching response speed may be fabricated at much smaller sizes than switching transistors having even modest fanout drive capability. The cross-sectional area of conductors (whether vias or lines) can have a substantial effect, through effects of its resistance and capacitance, on the signal propagation time through the conductor as well as thermal performance to remove heat from active devices.
Such optimization through change of size of elements, however, cannot generally be performed in a single lithographic level or device layer without substantially increased difficulty, process complexity or potential loss in manufacturing yield, as alluded to above. Formation of differently sized devices in different layers or at different lithographic levels increases conductor length (reducing performance) and number of process steps (increasing cost and tool overhead) while possibly compromising manufacturing yield.
It is theoretically possible to make compensations for lithographic patterning of features of increased feature size using an exposure tool optimized for a smaller minimum feature size. However, a different compensation, including a relatively large number of interrelated parameters must be calculated, approximated or extrapolated for each larger size desired and often provides irregular or unpredictably non-uniform results. Therefore, return on such additional costs is highly unpredictable and may result in large losses of manufacturing yield.
It is also theoretically possible to develop differently sized features in a single layer with different lithographic processes and differently optimized tools. However, at high integration densities, alignment of exposures is especially critical and difficult to reliably achieve with different tools or a single tool operated with different sets of optimized parameters. Much the same is true for seeking to develop larger features from multiple exposures of smaller shapes which greatly increases total lithographic exposure time as may be compromised by incorrect stitching together of the smaller shapes. Again, process cost and complexity is increased and manufacturing yield may be compromised.
Accordingly, at the present state of the art, no process is available to allow reliable production of features of sizes differing in sufficient degree to allow performance optimization consistent with currently possible and foreseeable minimum feature sizes in integrated circuit designs. Therefore, a trade-off between cost and manufacturing yield and near-optimal performance has been unavoidable at high integration densities and imposes a practical limit on integration density in integrated circuits.
It is therefore an object of the present invention to provide a method of reliably producing lithographic features of differing sizes in the same lithographic level consistent with optimization of exposure tools to produce currently possible and foreseeable feature sizes in order to improve and/or enhance performance of integrated circuit designs fabricated therewith.
It is another object of the invention to provide reliably manufacturable, maximal density, integrated circuits capable of enhanced performance by virtue of having features of different sizes in the same lithographic level or device layer.
In order to accomplish these and other objects of the invention, a method of fabricating a semiconductor device is provided including steps of patterning a resist to form a first mask pattern, transferring the first mask pattern to an underlying layer of material, block-out masking a portion of the resist, modifying a portion of the first mask pattern transferred to the underlying layer of material in accordance with the block-out masking to form a second mask pattern, transferring the second mask pattern to a further underlying layer of material to form openings therein, and completing the semiconductor device.
In accordance with another aspect of the invention, a lithography mask is provided by a process including steps of patterning a resist to form a first mask pattern, transferring the first mask pattern to an underlying layer of material, block-out masking a portion of the resist, and modifying a portion of the first mask pattern transferred to the underlying layer of material in accordance with the block-out masking to form a second mask pattern.
In accordance with a further aspect of the invention, a semiconductor device is provided including a first feature of a first size in a layer thereof, the first size being a minimum feature size in the layer, and a second feature of a second size larger than the first size in the same layer of the semiconductor device.